1. Field of the Invention
The present invention generally relates inverter circuits, and more specifically to an oscillator circuit including multiple inverter circuits that are insensitive to changes in the power supply voltage.
2. Description of the Related Art
Jitter in clock networks and phase locked loop (PLL) oscillators is a significant problem in conventional integrated circuits. A major source of jitter in clock networks and PLL oscillators is due to modulation of the power supply voltage provided to inverters that are used as buffers or delay elements. In operation, the power supply voltage may vary by as much as 100 or more millivolts.
FIG. 1A illustrates a conventional prior art inverter circuit 100 with two-complementary metal oxide semiconductor (CMOS) transistors and VDD provided as the power supply. FIG. 1B illustrates the relationship between the transition delay from the input (In) to the output (out) and VDD of the prior art inverter circuit 100 shown in FIG. 1A. When VDD has a value between a minimum operating VDD and a maximum operating VDD for the inverter 100, the input/output (transition) delay decreases as the voltage of VDD increases. In other words, the speed of the inverter 100 increases as the voltage of VDD increases.
FIG. 1C illustrates a prior art ring oscillator circuit including three inverters 100 configured to generate a clock output Q. When the voltage of VDD changes, the transition delay through the inverters also changes, producing jitter in the clock output of the ring oscillator, Q. FIG. 1D illustrates jitter of the ring oscillator circuit output Q caused by changes in the power supply voltage VDD. As VDD decreases, the transition delay for the inverters 100 increases, reducing the frequency of the clock output Q.
Accordingly, what is needed in the art is a mechanism for reducing jitter caused by changes in a power supply voltage for a clock generated by a ring oscillator of inverter devices.